1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a boost potential generation circuit and, in particular, a semiconductor memory device having a boost potential generation circuit for boosting a power supply voltage fed from an outside and applying it to a word line drive system circuit.
2. Description of the Related Art
For a dynamic random access memory (hereinafter referred to as a DRAM) it is necessary to refresh stored data in a memory cell in a predetermined time interval. The refresh cycle is determined by an external specification. The refresh cycle is of one kind for a 1M bit and a 4M bit DRAM and a plurality of kinds for over 16M bit DRAM according to the specification. In the 64M bit DRAM, for example, three kinds of refresh cycles are set on the specification: 2048, 4096, 8192 refresh cycles. When the number of refresh cycles varies, the number of word lines selected at a time at one refresh cycle varies correspondingly. In a 2048-refresh cycle product, four times the number of word lines are simultaneously selected on a 8192 refresh cycle product.
In a semiconductor memory device including a boost potential generation circuit for boosting a power supply voltage fed from an outside and supplying it to a word line drive system circuit and adapted to drive associated word lines with the use of the output of the boost potential generation circuit, a ratio between the number of simultaneously selected word lines and the current supply capability of the boost potential generation circuit for driving the word lines varies in accordance with the specification of the refresh cycle. In other words, for a refresh cycle product varying in potentials on the word lines in accordance with the refresh cycle specification and having more number of simultaneously selected word lines (or low refresh cycle), there is a risk that data access to and from the memory cell will become incomplete.
A semiconductor memory device for driving word lines with the use of an output of the above-mentioned boost potential generation circuit is disclosed, for example, in 1990 Symposium on VLSI Circuits pp. 17-18, "A 1.5 V Circuit Technology for 64 Mb DRAMs" Y. Nakagome et al. It may be considered that a plurality of kinds of chips be formed with the current supply capability of the boost potential generation circuit varied for each refresh cycle so as to correspond to the above-mentioned refresh cycle and current supply capability of the boost potential generation circuit for word line drive. However, the use of more kinds of chips lead to a greater drop in the development efficiency and in production efficiency.
For the semiconductor memory device, the change of refresh cycles is made, by the use of switching means such as wire bonding and fuses, so as to handle more kinds of chips. The technique for varying the number of refresh cycles and word line potential boosting capacity by the switching means is disclosed in Japanese Patent Application 4-221694 filed by the same applicant as that of the present application and corresponding to U.S. patent application Ser. No. 07/935,174. As a boost potential generation circuit for driving the word lines of a DRAM, use has been made of the usual method called "the bootstrap method". In this technique, potential boosting is achieved by supplying a drive signal to a precharged capacitor. In this case, a plurality of kinds of chips different in their refresh cycles are manufactured from one kind of chip by varying the capacitance (word line potential-boosted capacitance) of a bootstrap circuit in accordance with the refresh cycle.
A recent tendency has been made toward lowering a power supplying voltage in the semiconductor memory device. In the detail, shifting has been made from the conventional 5 V system to a 3.3 V or a 3 V system. With the lowering of the power supply voltage, there is a risk that a boost potential on the word line will not be able to be adequately increased in the conventional bootstrap system.
As one solution to this problem, proposals have been made to steadily generate a boost potential and use it as a power supply for a word line drive circuit. As a method for steadily generating the boost potential, use has principally made of one utilizing a charge pump circuit. In this case, however, there arises a variation in an internal potential, that is, in the output of the boost potential generation circuit. If the current supply capability of the charge pump circuit becomes greater, the lowering of the internal potential is prevented at the time of operating the internal circuit, but there arises a variation (ripple) in the boost potential resulting from the operation of the charge pump. If the current supply capability of the charge pump circuit is made small, the ripple becomes small but there occurs a greater drop at the time of operating the internal circuit acting as a load for the charge pump circuit. In this case, it is necessary that the current supply capability of the internal potential boosting circuit be made greater than, but not excessively, than the current required at a time of operating the internal circuit acting as a load.
In the case where, in the conventional semiconductor integrated circuit, particularly, a semiconductor memory device, there occurs a variation in current supply capability required of the boost potential generation circuit, the current supply capability of the boost potential generation circuit has been so set as to correspond to the case where current supply capability is the greatest at the low refresh cycle. With the current supply capability so set, the current supply capability of the boost voltage generating circuit becomes excessive at the high refresh cycle, thus presenting a problem with a greater ripple in the internal potential. In order to prevent any ripple, a greater load capacitance be connected to the boost potential output terminal. The use of a greater load capacitance leads to an increase in the size of the chip and an eventual fall in reliability.